1. Field of the Invention
The present invention relates to the packaging of semiconductor devices and, more particularly, to the use of wafer-scale bonding techniques in the packaging of microelectromechanical systems (MEMS).
2. Background
MEMS devices have been manufactured in the past using integrated circuit (IC) fabrication techniques. Although MEMS devices are generally fabricated on silicon wafers, MEMS devices are different from most ICs in that they possess moving elements. These moving elements make MEMS devices vulnerable to contamination and moisture because they cannot be encapsulated in a typical injection-molded plastic package, i.e., at least one element of every MEMS device must remain free to move.
Several specialized methods, which are directed to different stages of the fabrication process, have been employed for the sealing and packaging of MEMS. One early method directed to the final packaging stage employs a ceramic package with a co-fired lead frame, a cavity to contain a complete MEMS device and a lid to cover the package and cavity. With this chip-scale packaging method, the MEMS device is placed inside the cavity and the lid is soldered in place to form a hermetic seal. One problem with this chip-scale packaging approach is the expense associated with handling the individual components (e.g., the packages, lids, etc.) and assembling them into a single package. An additional problem with this chip-scale packaging approach is that the moving elements in MEMS are extremely fragile and tend to be damaged by any handling, especially near the end of the fabrication process. Therefore, packaging yields are typically low. A further problem with this packaging approach is that the solder seal on the lid tends to outgas when re-flowed during the final sealing process. If a vacuum is needed inside the package, a getter must be added, at additional cost. In such cases, packaging costs can constitute 80% of the total device cost. In sum, the use of ceramic packages to seal and package MEMS devices is inordinately expensive due to the need to individually handle components, the need to use getters and the considerable opportunity for damage and contamination of the MEMS devices.
A wafer-scale pre-packaging technique of bonding two wafers together has been used to bond a wafer of silicon or glass onto a MEMS wafer. In this back-end process, a non-conductive glass frit is screen-printed onto a lid wafer in the shape of rings or gaskets. The wafers are then placed together to form cavities containing MEMS devices and bonded by the application of heat in excess of 400° C. After bonding, the two-wafer stack is diced and the resulting hybrid structures are packaged in the standard manner: by encapsulation in plastic packages such as DIPs, SOICs, etc. Although this process has been marginally successful, it suffers from the deficiency that the glass frit cannot be patterned into fine features. Typically, gasket pattern line widths are between 100-200 microns. Given that MEMS are currently made with dimensions or features in the one-micron size range, significant real estate must be sacrificed, thereby significantly reducing the number of devices that can be fabricated on a single wafer. Attempts have been made to improve the glass frit patterning resolution, using lithographic methods, but these have not shown success. Further, gasket patterns thinner than 100-200 microns in width do not appear to provide reliable hermetic seals, possibly because of the inherently porous nature of glass frits. Thus, it is currently believed that glass frit techniques simply cannot be applied on a smaller scale where hermetic seals are desired.
Glass frit techniques also require high temperatures of between about 450-600 Celsius for sealing to occur. One drawback of using such a high firing temperatures is that it effectively precludes the incorporation of integrated circuitry on either of the wafers bonded together. These temperatures also preclude the use of most anti-stiction coatings and hydrophobic coatings, which are desirable for improving manufacturing yields and the MEMS's tolerance to moisture and shock. Such high temperatures also damage the MEMS themselves and, particularly, certain structural films deposited at lower temperatures and structures in which the film stress must be carefully controlled.
Another deficiency of glass frit techniques is that the glass frit itself employs organic binders that outgas into the sealed cavity during firing. Since getters are not available to combat this problem, this fact precludes the use of glass frits for vacuum applications. Still another limitation of the glass frit techniques is that the sealing materials, being non-conductive, cannot be used to establish electrical coupling between the devices disposed on the bonded substrates.
Front-end wafer-scale bonding techniques which can be used for sealing MEMS have also been developed, including anodic bonding, silicon fusion bonding, and other wafer-bonding methods employing combinations of silicon, silicon dioxide, and silicon nitride. These techniques can provide vacuum and hermetic seals and can do so with improved use of device real estate. These techniques, however, have low throughput and require high temperatures for high-quality bonds because their bonding mechanisms involve solid diffusion across the bond interface. Additionally, these techniques place strict constraints on the materials and processes used to form the wafers to be bonded together. Wafer-scale bonding techniques are exceptionally sensitive to the presence of small particulate contaminants, wafer warpage, scratches, and other imperfections commonly encountered during semiconductor fabrication because such contaminants can cause large defects in the bond and reduce yield substantially. Moreover, normal variations in surface topology due to the presence of circuitry can preclude proper bonding and/or sealing using such techniques. All of these factors make it difficult to employ wafer-bonding techniques with wafers that have undergone a significant amount of processing (e.g., wafers bearing finished microstructures).
One micro-switch. The micro-switch can be used in, for example, mobile phones for switching RF signals between transmit and receive modes and other related functions. Additional applications include micro-relays, which can be used in, for example, automated test equipment (ATE). As will be described below with respect to FIGS. 1a and 1b, fabricating a hermetically sealed micro-switch using materials having good mechanical qualities is difficult to achieve using prior art front-end, wafer-scale bonding techniques.
Referring to FIGS. 1a and 2b, there are shown cross-sectional views of a prior art MEMS device 100 configured to operate as a micro-switch (hereinafter also referred to as “micro-switch 100”). FIG. 1a is a cross-sectional view of the micro-switch 100 in its “deactivated” state (i.e., no electric field 118 present) and FIG. 1b is a cross-sectional view of the micro-switch 100 in its “activated” state (i.e., electric field 118 present).
The micro-switch 100 includes substrate 102, pedestal 104, actuator 106, cantilever 108, contact pad 110, and signal path 112. The substrate 102 is typically made of silicon and provides a support base for the pedestal 102 and the cantilever 108. The pedestal 102 and the cantilever 108 are formed in different layers upon the substrate 102 using known IC fabrication processes (e.g., CMOS). The pedestal 104 is disposed on the substrate 102. It provides support for the cantilever 108 and also provides a sidewall 114, which together with the cantilever 108 and the substrate 102 defines a gap 116. The gap 116 is typically very small (e.g., on the order of 2 microns in the vertical dimension). It provides the cantilever 108 with at least one degree of freedom.
The contact pad 110 is disposed on a free end (distal end) of the cantilever 108 and is typically made of metal. The location of the contact pad 110 on the cantilever 108 is selected to ensure that it makes electrical contact with the signal path 112, when the actuator 106 is activated and the cantilever 108 is pulled downward towards the substrate 102 in response to an electric or magnetic field 118, as shown in FIG. 1b. 
The signal path 112 is disposed on the substrate 100 in aligned opposition with the contact pad 110. It is typically a metal trace or strip, which serves as a path for signals propagating through the micro-switch 100. The signal path 112 includes a gap (not shown) in a location corresponding to the location of the contact pad 110 on the cantilever 108. If the actuator 106 is inactive, a signal launched into the signal path 112 cannot propagate through the micro-switch 100 due to the gap.
The actuator 106 is disposed on the substrate 100. It establishes a field 118 (shown in FIG. 1b) when supplied with a drive voltage. The field 118 provides a force that pulls the cantilever 108 downward toward the substrate 102, until the contact pad 110 bridges the gap in the signal path 112. In this “activated” state, a signal launched into the signal path 112 will propagate through the micro-switch 100 due to the bridged gap 116 provided by the contact pad 110. FIG. 1b shows the cantilever 108 pulled into electrical contact with the signal path 112, thereby bridging the gap to allow signals to propagate through the micro-switch 100.
It would be desirable to fabricate the prior art cantilever 108 from materials that exhibit good mechanical qualities. One example of such material is polycrystalline silicon (“polysilicon’), which has been extensively studied and is known to be a desirable material for fabricating micromechanical devices. Polysilicon, however, is not generally used to fabricate prior art switches (e.g., micro-switch 100), because the cantilever 108 is designed to lie over the contact pad 110, and therefore must be deposited on the substrate 102 after the contact pad 110 in the fabrication process flow. The high temperature of the polysilicon anneal (e.g., above 400° C.) may cause the contact pad 110 to melt, delaminate, or interdiffuse with other material layers, thus making polysilicon an unsuitable material for the cantilever 108.
This problem was addressed in the past by using low temperature deposited materials, such as PECVD silicon nitride. The disadvantage with this prior art technique is that a high temperature anneal is typically needed to control warping of the cantilever 108 due to stress gradients. The degree of warping (curling of the cantilever 108 up or down with respect to the substrate 102) is not easily controlled and leads to wide variations in the voltage required to actuate the cantilever 108. This is typically not acceptable in a mass-produced device.
Accordingly, there is a need for a novel wafer-scale bonding technique that can employ materials having desirable mechanical qualities. Such a technique should enable massive, parallel assembly of hermetically sealed, low-cost MEMS devices, and thus should provide high yields. To realize these advantages, the technique should not require extreme wafer planarity or cleanliness. Additionally, there is a need for an improved micro-switch/relay device, fabricated using the novel wafer-scale bonding technique from materials having desirable mechanical qualities, to provide improved performance and reliability over prior art MEMS devices.